Towards Debug Automation for Timing Bugs at RTL
نویسندگان
چکیده
One major concern in the design of Very-Large-Scale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug timing bugs at the design step. The approach utilizes Boolean Satisfiability (SAT) in order to model design timing bugs at the pre-silicon stage. The experimental results show diagnosis accuracy and efficiency of the approach. Keywords—debug automation, timing bug, diagnosis accuracy
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